1. Field of the Invention
The present invention relates generally to the fabrication of integrated circuits, and more particularly to a method for forming contact vias in integrated circuits.
2. Description of the Prior Art
By increasing the density of components in an integrated circuit, it has become necessary to fabricate multilevel metal interconnect and contacts between the layers. To maintain the integrity of the layers of metal interconnect and contacts, insulating layers must be formed between each metal interconnect layer. Fabricating multiple layers, however, results in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross sections when crossing over uneven topography. This can lead to portions of the metal interconnect lines having a higher current density or voids in the lines themselves. These defects can cause electromigration or other related device failure mechanisms.
Various techniques are used during the fabrication process to planarize the surface of the integrated circuit. One method involves depositing a layer of spin on glass over an insulating layer. The spin on glass is then etched back so that portions of the spin on glass remain in the lower topographical regions of the insulating layer. This planarizes the surface of the integrated circuit. A problem arises, however when forming contact vias between metal interconnect lines. When forming a metal contact within the contact via, the spin on glass can contaminate the metal contact. This can cause step coverage problems or increased resistivity in the contact.
Therefore, it would be desirable to provide a method for fabricating contact vias in integrated circuits which do not have planarizing material therein. It is also desirable that such a method not significantly increase the complexity of the manufacturing process.